mips64emul |
Technical Documentation |
This page describes some of the internals of mips64emul. For more general documentation, please read the User Documentation.
NOTE: This page is under construction.
In reality, a lot of things need to be handled. Before each instruction is executed, the emulator checks to see if any interrupts are asserted which are not masked away. If so, then an INT exception is generated. Exceptions cause the program counter to be set to a specific value, and some of the system coprocessor's registers to be set to values signifying what kind of exception it was (an interrupt exception in this case).
Reading instructions from memory is done through a TLB, a translation lookaside buffer. The TLB on MIPS is software controlled, which means that the program running inside the emulator (for example an operating system kernel) has to take care of manually updating the TLB. Some memory addresses are translated into physical addresses directly, some are translated into valid physical addresses via the TLB, and some memory references are not valid. Invalid memory references cause exceptions.
When an instruction is read from memory, the emulator checks which opcode it contains and executes the instruction. Executing an instruction usually involves reading some register and writing some register, or perhaps a load from memory (or a store to memory). The program counter is increased for every instruction.
Some memory references point to physical addresses which are not in the normal RAM address space. They may point to hardware devices. If that is the case, then loads and stores are converted into calls to a device access function. The device access function is then responsible for handling these reads and writes. For example, a graphical framebuffer device may put a pixel on the screen when a value is written to it, or a serial controller device may output a character to stdout when written to.